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 HD74HC390
Dual Decade Counters
REJ03D0624-0200 (Previous ADE-205-503) Rev.2.00 Mar 30, 2006
Description
The HD74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-by-five counter. The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual bi-quinary, or various combinations up to a single divide-by-100 counter. The HD74HC390 is incremented on the high to low transition (negative edge) of the clock input, and each has an independent clear input. When clear is set high all four bits of each counter are set to a low level. This enables count truncation and allows the implementation of divide-by-N counter configurations.
Features
* High Speed Operation: tpd (Clock A to QA) = 11 ns typ (CL = 50 pF) * High Output Current: Fanout of 10 LSTTL Loads * Wide Operating Voltage: VCC = 2 to 6 V * Low Input Current: 1 A max * Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) * Ordering Information
Part Name HD74HC390P HD74HC390FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) P Package Abbreviation -- EL (2,000 pcs/reel) Taping Abbreviation (Quantity)
PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability.
Function Table
Clock A X B X X Clear H L L Operation Clear /2 and /5 Increment /2 Increment /5
Note:
X 1. H; High level, L; Low level, X; Irrelevant, Z; High impedance
Rev.2.00 Mar 30, 2006 page 1 of 6
HD74HC390
Pin Arrangement
1A 1Clear 1QA Output 1B 1QB
Outputs
1 2 3 4 5 6 7 8 (Top view)
CLR 1QA 1A 1B 1QB CLR 2QA 2A 2B 2QB 2QC
16 VCC 15 2A 14 2Clear 13 2QA Output
12 2B 11 2QB 10 2QC 9 2QD
Outputs
1QC 1QD GND
1QC
1QD
2QD
Logic Diagram
Clear A CK D Q CK R Q A B CK D Q CK R Q B
CK D Q
CK R Q C
CK D Q
CK R Q D
Rev.2.00 Mar 30, 2006 page 2 of 6
HD74HC390
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Symbol VCC VIN, VOUT IIK, IOK IOUT ICC or IGND PT Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 Unit V V mA mA mA mW
Storage temperature Tstg -65 to +150 C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note:
*1
Symbol VCC VIN, VOUT Ta tr , tf
Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500
Unit V V C ns
Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 Output voltage VOH 2.0 4.5 6.0 4.5 VOL 6.0 2.0 4.5 6.0 4.5 6.0 Input current Quiescent supply current Iin ICC 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 IOH = 4 mA IOH = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A V V Vin = VIH or VIL IOH = -20 A V Test Conditions
VIL
V
IOH = -4 mA IOH = -5.2 mA Vin = VIH or VIL IOL = 20 A
Rev.2.00 Mar 30, 2006 page 3 of 6
HD74HC390
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25C Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Pulse width tw 2.0 4.5 6.0 2.0 4.5 6.0 Output rise/fall time Input capacitance tTLH tTHL Cin 2.0 4.5 6.0 -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 25 5 4 -- -- -- -- Typ -- -- -- -- 11 -- -- 32 -- -- 16 -- -- 20 -- -- 15 -- -- 14 -- -- 8 -- -- 1 -- -- 5 -- 5 Max 5 27 32 120 24 20 290 58 49 130 26 22 185 37 31 130 26 22 165 33 28 -- -- -- -- -- -- 75 15 13 10 Ta = -40 to +85C Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 31 6 5 -- -- -- -- Max 4 21 25 150 30 26 365 73 62 165 33 28 230 46 39 165 33 28 205 41 35 -- -- -- -- -- -- 95 19 16 10 ns ns ns Clock B to QD ns ns Clock A to QA Unit MHz Test Conditions
ns
Clock A to QC (QA connected to Clock B) Clock B to QB
ns
Clock B to QC
ns
Clear to QA, QB, QC, QD
Removal time
th
ns
pF
Test Circuit
VCC VCC Output QA QB QC Clear QD CL = 50 pF
See Function Table
Input Pulse Generator Zout = 50 Input Pulse Generator Zout = 50
A B
Output Output Output
CL = 50 pF CL = 50 pF CL = 50 pF
Note : 1. CL includes probe and jig capacitance.
Rev.2.00 Mar 30, 2006 page 4 of 6
HD74HC390
Waveforms
* Waveform - 1
tr tf VCC Clock
50% 50% 50% 50%
tw
tw tPHL (Measure at tn+2)
90% 50% 10%
0V tPLH (Measure at tn+1)
90% 50% 10%
VOH VOL VOH VOL
QA
tTHL tPHL (Measure at tn+4)
90% 50% 10%
tTLH tPLH (Measure at tn+2)
90% 50% 10%
QB
tTHL tPHL (Measure at tn+8)
90%
tTLH tPLH (Measure at tn+4)
90% 50% 10%
VOH VOL
QC
50% 10%
tTHL tTLH tPHL (Measure at tn+10) tPLH (Measure at tn+8)
90% 90% 50% 10% 50% 10%
VOH VOL
QD
tTHL
tTLH
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. tn is bit time with all outputs at low.
* Waveform - 2
tr 90 % 50 % 50 % 10 % t w(clear) t PHL
90%
tf VCC 10 % 0V
Clear
VOH 50 %
10%
QA to QD
VOL
tTHL Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 5 of 6
HD74HC390
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
A1
A
E
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
( Ni/Pd/Au plating )
e1 D E A A1 bp b3 c e Z L
Nom Max 7.62 19.2 20.32 6.3 7.4 5.06
L
0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.12 2.54
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
8 bp x M L1
Reference Symbol
c
Dimension in Millimeters
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
Rev.2.00 Mar 30, 2006 page 6 of 6
A
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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(c) 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .6.0


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